The ALU

I completed week 2 and week 3 of the Nand to Tetris course which had me dealing with combinatorial logic and then sequential logic. The course simplified the sequential portion by giving us a pre-made data flip-flop chip to integrate. After figuring out the process of dealing with combinatorial logic it was fairly easy to implement the ALU through a series of multiplexers and pre-computing various values.. Then moving onto the concepts of sequential logic it was trivial to implement increasingly sized memory chips by composing de-multiplexer and mux chips along with any number of registers or smaller sized memory chips.

One of the interesting things that occurred to me during these projects was the fact that in hardware you must pre-compute all possible outputs and then select the appropriate output using a multiplexer. This is quite different in my mind from software thinking where you never want to compute a value unless you have to. The result is using conditional logic to prevent calling unneeded functions/methods and preventing the CPU from performing unnecessary work. However, for hardware, if you have a chip that can perform multiple different operations and you are telling it which operation to perform, you still have to compute all possible outputs in some manner, and then use selection via a Multiplexor to select the desired output. I’m not quite sure if this continues further into more complex hardware chips, but logically it made more sense to me to think of the hardware like this, and made it easier for me to logic through how to build the chips to obtain the desired output.

Next up, I will be dealing with writing the machine language.